There is an ever increasing demand in the semiconductor industry for smaller and faster transistors to provide the functionality of the ICs used in these devices. Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing ICs with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels). As such, smaller feature sizes, smaller separations between features such as gate length, and more precise feature shapes are needed. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of IC dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more IC die per semiconductor wafer.
Shortening of the gate length, however, tends to raise nonconformities such as time-dependent changes in the threshold voltage due to hot carriers and degradation of mutual conductance. As one solution for the problem, MOS transistors having a so-called extension structure (a lightly doped drain (LDD structure) is known. This LDD MOS transistor structure has a pair of impurity-diffused layers which are fabricated by forming shallow source and drain extension layers, forming side walls or the like as being attached to a gate electrode, and then forming deeper source and drain regions so as to partially overlap the extension region. LDD structures can be used for both NMOS and PMOS transistors.
NMOS transistor performance in advanced CMOS integrated circuits can be enhanced by a process sequence known as the stress memorization technique (SMT), in which a layer of tensile material is deposited on the wafer after the NMOS source and drain (NSD) ion implantation process is performed and before the source/drain anneal. The SMT film may include nitride that is deposited by plasma enhanced chemical vapor deposition (PECVD), and a relatively thin oxide layer deposited under the nitride layer. An example may be that the nitride layer is about 500 Å thick and the oxide layer may then be about 100 Å thick. In the case of polysilicon gates, during the source/drain anneal, the polycrystalline silicon (poly silicon) in the NMOS gate, which became partially amorphized by the NSD ion implant, recrystallizes with a grain configuration that exerts stress on the underlying NMOS channel region when the tensile layer is removed. The resultant strain in the NMOS channel increases the mobility of the charge carriers, which improves the on-state current capability of the NMOS transistors.
However, SMT processing can degrade the performance of PMOS transistors. Degradation of PMOS transistors by SMT can occur because hydrogen in the tensile film can enhance boron diffusion in the PMOS source and drain regions which can increase short channel effects and also enhance the diffusion of boron through the PMOS gate dielectric into the channel region which can also increase short channel effects and degrade hole mobility in the channel due to increased dopant scattering. The boron penetration problem may be particularly severe for silicon oxide-based gate dielectrics that have a low concentration (e.g., <5 at. %) of nitrogen. Short channel effects increase PMOS transistor standby power which is undesirable. Moreover, SMT can increase density of interface states on the PMOS transistor causing additional hole carrier mobility degradation and reduction in on-state current capability. Although the SMT layer can be selectively removed from the PMOS transistors before source/drain anneal to avoid these detrimental effects on PMOS transistor performance, selective removal increases manufacturing cost and cycle time.